Circuit device and manufacturing method therefor

ABSTRACT

A circuit device is made smaller in higher. The circuit device includes a wiring substrate, a first circuit element, and a second circuit element. The circuit substrate includes an insulating resin layer, a wiring layer provided on a main surface of the insulating resin layer, and a wiring layer provided on the other main surface of the insulating resin layer. The wiring layer includes first interconnectors to which the first circuit element connects, and wiring portions. The film thickness of the first interconnector is made thinner than that of the wiring portion. The wiring layer includes second interconnectors and wiring portions. The first interconnectors and the second interconnectors are connected through the medium of conductors.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority fromthe prior Japanese Patent Application No. 2007-146244, filed on May 31,2007, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a circuit device and a method formanufacturing the circuit devices.

2. Description of the Related Art

Portable electronic devices, such as mobile phones, PDAs, DVCs and DSCs,are gaining increasing sophistication in functions and features. And tobe accepted by the market, they have to be smaller in size and lighterin weight, and for the realization thereof, there is a growing demandfor highly-integrated system LSIs. On the other hand, these electronicdevices are desired to be easier or handier to use, and therefore theLSIs used in those devices are required to be more functionallysophisticated and better performing. For this reason, the higherintegration of LSI chips is causing increases in I/O count, which inturn generates demand for smaller packages. To satisfy both theserequirements, it is strongly desired that semiconductor packages suitedfor the high board density packaging of semiconductor components bedeveloped. To meet such needs, a variety of packaging technologiescalled CSP (Chip Size Package) are being developed.

With the downsizing of portable electronic devices accomplished so far,further reduction in the thickness of a circuit device is desired. Forexample, making a circuit device, used in the mobile phone, thinner by afew μm can sufficiently contribute to the further downsizing of themobile phone.

SUMMARY OF THE INVENTION

The present invention has been made in view of the foregoing problems tobe resolved, and a general purpose thereof is to provide a technologyfor making a circuit device smaller in height.

One embodiment of the present invention provides a circuit device. Thecircuit device comprises: a substrate; a first wiring layer including afirst interconnector and a wiring portion provided on one face of thesubstrate; a second wiring layer including a second interconnectorprovided on the other face of the substrate; a conductor, penetratingthrough the substrate, which electrically connects the firstinterconnector and the second interconnector; and a circuit elementmounted on the first interconnector, wherein the film thickness of thefirst interconnector is less than that of the wiring portion.

In the circuit device according to the above-described embodiment, thesecond interconnector may be covered with a metal whose ionizationtendency is smaller than that of a metal forming the firstinterconnector.

In the circuit device according to the above-described embodiment, thecircuit element may be flip-chip connected to the first interconnector.

Another embodiment of present invention provides a method formanufacturing a circuit device. The method for manufacturing a circuitdevice comprises: forming a first wiring layer which includes a firstinterconnector on one face of a substrate; forming a second wiring layerwhich includes a second interconnector electrically connected to thefirst interconnector, the second interconnector being provided on theother face of the substrate; covering the second interconnector with ametal whose ionization tendency is smaller than that of a metal formingthe first interconnector; forming a pre-flux film on a surface of thefirst interconnector by subjecting the first interconnector to anorganic solderability preservative processing; and mounting a circuitelement on the first interconnector.

In the method for manufacturing a circuit device according to theabove-described embodiment, a metal forming the first interconnector maybe copper and a metal covering the second interconnector may be gold.

It is to be noted that any arbitrary combinations or rearrangement, asappropriate, of the aforementioned constituting elements and so forthare all effective as and encompassed by the embodiments of the presentinvention.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments will now be described by way of examples only, withreference to the accompanying drawings which are meant to be exemplary,not limiting, and wherein like elements are numbered alike in severalFigures in which:

FIG. 1 is a cross-sectional view of a circuit device according to anembodiment of the present invention;

FIGS. 2A to 2C are cross-sectional views showing a process in a methodfor manufacturing a circuit device according to an embodiment of thepresent invention;

FIGS. 3A and 3B are cross-sectional views showing a process in a methodfor manufacturing a circuit device according to an embodiment of thepresent invention; and

FIG. 4 is a cross-sectional view showing a process in a method formanufacturing a circuit device according to an embodiment of the presentinvention.

DETAILED DESCRIPTION OF THE INVENTION

The invention will now be described by reference to the preferredembodiments. This does not intend to limit the scope of the presentinvention, but to exemplify the invention.

The embodiments will now be hereinafter described with reference todrawings.

FIG. 1 is a cross-sectional view of a circuit device according to anembodiment of the present invention. A circuit device 10 includes awiring substrate 20, a first circuit element 30, and a second circuitelement 40.

The wiring substrate 20 is a two-layered substrate that includes aninsulating resin layer 22 serving as a core, a wiring layer 50 providedon one face (hereinafter referred to as surface L1) of the insulatingresin layer 22, and a wiring layer 60 provided on the other face(hereinafter referred to as surface L2) of the insulating resin layer22.

The material used for the insulating resin layer 22 is, for instance, amelamine derivative, such as BT resin, or a thermosetting resin, such asliquid-crystal polymer, epoxy resin, PPE resin, polyimide resin,fluorine resin, phenol resin or polyamide bismaleimide. From theviewpoint of improving the heat radiation of the circuit device 10, itis preferable that the insulating resin layer 22 has a high thermalconductivity. In this respect, it is desirable that the insulating resinlayer 22 contains, as a high thermal conductive filler, silver, bismuth,copper, aluminum, magnesium, tin, zinc, or an alloy thereof.

The wiring layer 50 includes first interconnectors 52 and wiringportions 54. As a material used for the wiring layer 50, a metal such ascopper is used, for instance. More preferably, a rolled copper is usedas the material for the wiring layer 50.

The first interconnector 52 is a terminal on which the first circuitdevice 30 is mounted. The film thickness of the first interconnector 52is less than that of the wiring portion 54. That is, the firstinterconnector 52 is thinned as compared with the wiring portion 54.

The wiring portion 54 is provided in an area where no circuit device ismounted thereon. Of the wiring portion 54, a connection terminal part 55used for the wire bonding connection is covered with a gold platinglayer 56. The structure having the gold plating layer 56 like this cansuppress the deterioration of connection terminal part 55 in the wiringportion 54.

A protective film (solder resist) 58 where the areas thereof coveringthe first interconnectors 52 and the connection terminal parts 55 of thewiring portions 54 serve as openings is formed on the surface L1 of theinsulating resin layer 22.

The wiring layer 60 includes second interconnectors 62 and wiringportions 64. As a material used for the wiring layer 60, a metal such ascopper is used, for instance. More preferably, a rolled copper is usedas the material for the wiring layer 60.

The second interconnector 62 is used as a terminal for mounting thecircuit device 10 on a motherboard. The second interconnector 62 iscovered with a gold plating layer 66. A protective film (solder resist)68 where the areas thereof covering the second interconnectors 62 serveas openings is formed on the surface L2 of the insulating resin layer22.

The wiring portion 64 is a rewiring necessary for the repositioning ofthe second interconnector 62. According to the present embodiment, thethickness of the second interconnector 62 is equal to that of the wiringportion 64.

A conductor 70 penetrates the insulating resin layer 22, therebyconnecting electrically the first interconnector 52 and the secondinterconnector 62. A material that constitutes the conductor 70 may becopper, silver paste or copper paste, for instance.

The first circuit element 30 is mounted on the surface L1 of theinsulating resin layer 22. The first circuit element 30 may be an IC orLSI, for instance. According to the present embodiment, the firstcircuit element 30 is flip-chip connected in a manner such that anelectrode forming face thereof is placed downward. More specifically, anexternal electrode 32 formed on the first circuit element 30 iselectrically connected to the first interconnector 52 provided on thewiring substrate 20 through the medium of a bump 34.

The second circuit element 40 is mounted on the first circuit element 30through the medium of a bonding material such as die-attach film. Thesecond circuit element 40 may be an IC or LSI, for instance. An externalelectrode 42 of the second circuit element 40 is connected to theconnection terminal part 55 in the wiring portion 54 by a wire bondingusing a gold wire 44.

By employing the circuit device 10 described as above, the firstinterconnector 52 is thinner than the wiring portion 54. Thus the heightof the circuit device 10 including the first circuit element 30, mountedon the first interconnector 52, and the second circuit element 40,mounted on the first element 30, can be made smaller. That is, thecircuit device 10 can be made smaller in height.

The amount of metal (i.e., “copper” in the embodiment) provided on thesurface L1 of the insulating resin layer 22 is reduced by a reduction inthickness of the first interconnector 52 relative to the wiring portion54. This reduces warping of the circuit device 10, thereby enhancing thereliability of the circuit device 10 mounted on the motherboard.

Also, when the circuit device 10 is mounted on the motherboard, thedistance between the first circuit element 30 and the motherboarddecreases. Hence, the heat radiation property of the circuit device 10is enhanced.

(Manufacturing Method)

FIG. 2A to FIG. 4 are cross-sectional views illustrating processes in amethod for manufacturing a circuit device according to an embodiment.

As shown in FIG. 2A, copper foils 100 and 110 are press-bondedrespectively to one face of the insulating resin layer 22 and the otherface thereof. Rolled coppers may be used as the copper foils 100 and110.

Then, as shown in FIG. 2B, openings 102 are formed on the copper foil100 by an etching technique or the like in accordance with the positionsof the conductors. Then, through holes 104 are formed in the insulatingresin layer 22 by laser irradiation.

Then, as shown in FIG. 2C, the conductors 70 made of copper are formedin the through holes 104 by using an electroless plating method and anelectrolytic plating method. Then the copper foils 100 and 110 arepatterned by using a photolithography method and an etching method. Atthis stage, the film thickness of the copper foil 100 is kept constant.The thus patterned copper foil 100 becomes the first interconnectors 52and the wiring portions 54. Also, the thus patterned copper foil 110becomes the second interconnectors 62 and the wiring portions 64.

Then, as shown in FIG. 3A, a protective film 58 (solder resist film)where openings are provided at predetermined positions are formed on thesurface L1 of the insulating resin layer 22. After this, a connectionterminal part 55 in the wiring portion 54 and the second interconnector62 are covered with gold plating layers 56 and 66, respectively, bynickel-gold plating. It is preferable that a gold-resist be formed onthe copper excluding an area thereof where the gold plating layer needsto be formed. Subsequently, a protective film 68 where the areas thereofcovering the second interconnectors 62 serve as openings is formed onthe surface L2 of the insulating resin layer 22.

Next, as shown in FIG. 3B, the first interconnectors 52 undergo anorganic solderability preservative (OSP) processing. In the OSPprocessing, a pre-flux liquid where imidazole compounds are dissolvedinto a solvent are used, for instance. As a result of this OSPprocessing, a pre-flux film 59 of 0.5 μm to 2 μm thickness, for example,is formed on the surface of the first interconnector 52. The pre-fluxfilm 59 is formed as follows. The copper solved out of the firstinterconnector 52 reacts with the imidazole compounds so as to become acopper-imidazole complex. This forms the pre-flux film 59. Accordingly,the first interconnector 52 is so thin-filmed that it is thinner by thefilm thickness of the pre-flux film 59. On the other hand, the secondinterconnector 62 is covered with the gold plating layer 66 whoseionization tendency is smaller than that of copper, at portions comingin contact with pre-flux liquid. Hence, the second interconnectors 62are not affected by the OSP processing, so that the pre-flux films 59are formed only on the first interconnectors 52.

Next, as shown in FIG. 4, the first interconnectors 52 and the externalelectrodes 32 of the first circuit element 30 are connected by using thesolder bumps 34, and thereby the first circuit element 30 is flip-chipconnected to the wiring substrate 20. Further, the second circuitelement 40 is mounted on the first circuit element 30 via a bondingmaterial (not shown) such as a die-attach film. Then, the externalelectrodes 42 of the second circuit element 40 and the connectionterminal parts 55 in the wiring portions 54 are connected using goldwires 44. Through the processes as described above, a circuit device asshown in FIG. 1 is manufactured. As shown in FIG. 4, solder bumps 200may be formed on the second interconnectors 62 as necessary. Also, thecircuit device 10 may be packaged by a molded resin 210, using atransfer mold method or the like.

The present invention is not limited to the above-described embodiments,and it is understood by those skilled in the art that variousmodifications such as changes in design may be made based on theirknowledge and the embodiments incorporating such modifications are alsowithin the scope of the present invention.

Though the wiring substrate having a two-layer wiring structure as awiring layer is exemplified in the above-described embodiment, thewiring substrate may have multilevel interconnection of three or morelayers.

The metal that covers the second interconnector 62 is one whoseionization tendency is smaller than that of the metal constituting thefirst interconnector 52. Such a metal is not limited to gold, and themetal covering the second interconnector may be platinum, silver, lead,solder, or the like.

1-6. (canceled)
 7. A method for manufacturing a circuit device, themethod comprising: forming a first wiring layer which includes a firstinterconnector on one face of a substrate; forming a second wiring layerwhich includes a second interconnector electrically connected to thefirst interconnector, the second interconnector being provided on theother face of the substrate; covering the second interconnector with ametal whose ionization tendency is smaller than that of a metal formingthe first interconnector; forming a pre-flux film on a surface of thefirst interconnector by subjecting the first interconnector to anorganic solderability preservative processing; and mounting a circuitelement on the first interconnector.
 8. A method for manufacturing acircuit device according to claim 7, wherein a metal forming the firstinterconnector is copper and a metal covering the second interconnectoris gold.
 9. A method for manufacturing a circuit device according toclaim 7, wherein said mounting a circuit element is such that thecircuit element is connected to the first interconnector using a solderbump.
 10. A method for manufacturing a circuit device according to claim8, wherein said mounting a circuit element is such that the circuitelement is connected to the first interconnector using a solder bump.